[patch] Vypinani (poweroff) na SMP pocitacich

[Petr Novotny]

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On 18 Feb 00, at 22:47, Pavel Kankovsky wrote:
> (a stejne jsou Celerony ty PII, co neprosly vystupni kontrolou
> na 100% <g>)

:-) To byla myslenka dne. Udela se PII (bez L2 cache na chipu), 
vyzkousi se, a kdyz nefunguje, tak se k nemu na chip hodi L2 
cache a proda jako Celeron. :-O Nedelate u Intela v marketingu?

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--
Petr Novotny, ANTEK CS
Petr.Novotny na antek.cz
http://www.antek.cz
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